A system-on-chip (SOC) often includes components such as memory, one or more processors, and input/output (I/O) circuitry, all fabricated on a single integrated circuit die. SOCs can also include programmable logic circuitry such as that found in field programmable gate arrays (FPGAs). SOCs provide a variety of configuration parameters for regulating memory traffic and controlling the quality of service (QOS).
The quality of service (QOS) in accessing memory resources is often measured in terms of latency and bandwidth utilization. Latency is the amount of time from when a memory transaction is issued by a requester to when the requester receives data from a read transaction or an acknowledgement that a write transaction is complete. Memory bandwidth is the theoretical or advertised rate (e.g., bytes/second) at which data can be read from or written to the memory by one or more requesters, and bandwidth utilization is the percentage of the memory bandwidth consumed in processing memory transactions submitted in a system running a user's application.
Effectively regulating memory bandwidth allocation in an SOC amongst multiple requesters and traffic types can be challenging due to the complexity and variability of SOC architectures and the vast number of different applications that can be deployed on SOCs. In addition, the performance of a memory system relative to an individual one of the many control parameters is often non-linear as there are many factors beyond a single control parameter that can affect performance.